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Calling Line Identification Receiver
Features
* * * *
HT9032
HT9032B/C/D operating voltage: 3.5V~5.5V HT9032F operating voltage: 3.0V~5.5V Bell 202 FSK and V.23 demodulation Ring detection input and output Carrier detection output
* * *
Power down mode High input sensitivity HT9032C: 16-pin DIP/SOP package HT9032B/F-A: 8-pin DIP package HT9032D/F-B: 8-pin SOP package
Applications
* * *
Feature phones Caller ID adjunct boxes Fax and answering machines
* *
Computer telephony interface products ADSI products
General Description
The HT9032 calling line identification receiver is a low power CMOS integrated circuit designed for receiving physical layer signals transmitted according to Bellcore TR-NWT-000030 and ITU-T V.23 specifications. The primary application of this device is for products used to receive and display the calling number, or message waiting indicator sent to subscribers from the central office facilities. The device also provides a carrier detection circuit and a ring detection circuit for easier system applications.
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HT9032
Block Diagram
T IP R IN G B and P ass F ilte r D e m o d u la to r
PDW N PowerUp L o g ic
V a lid D a ta D e te c tio n
DOUTC DOUT CDET
R T IM E
In te rn a l PowerUp L o g ic RDET1 RDET2 R in g A n a ly s is C ir c u it RDET
VDD VSS
R e fe re n c e V o lta g e
C lo c k G e n e ra to r
X1 X2
Pin Assignment
T IP R IN G 2 3 4 5 6 7 8 RDET1 RDET2 T IP R IN G PDW N 3 6 4 5 VSS 2 7 1 8 VDD DOUT X1 X2 NC R T IM E PDW N VSS 1 16 15 14 13 12 11 10 9 VDD DOUTC DOUT CDET RDET NC X1 X2 DOUT VDD T IP 3 6 4 5 R IN G 2 7 1 8 X1 X2 VSS PDW N
HT9032B 8 D IP
HT9032C 1 6 D IP /S O P
HT9032D 8SOP
T IP R IN G PDW N 3 VSS 4 2
1 8 7 6 5
VDD DOUT CDET X1
DOUT VDD T IP 3 R IN G 4 2
1 8 7 6 5
CDET X1 VSS PDW N
H T 9 0 3 2 F -A 8 D IP
H T 9 0 3 2 F -B 8SOP
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HT9032
Pin Description
Pin Name I/O Power Inputs VDD VSS PDWN Clock X1 X2 I O A crystal or ceramic resonator should be connected to this pin and X2. This pin may be driven from an external clock source. A crystal or ceramic resonator should be connected to this pin and X1. It detects ring energy on the line through an attenuating network and enables the oscillator and ring detection. This is a schmitt trigger input. It couples the ring signal to the precision ring detector through an attenuating network. RDET=0 if a valid ring signal is detected. This is a schmitt trigger input. 3/4 3/4 I Power-VDD is the input power for the internal logic. Ground-VSS is ground connection for the internal logic. A logic 1 on this pin puts the chip in power down mode. When a logic 0 is on this pin, the chip is activated. This is a schmitt trigger input. Description
Ring Detections RDET1 RDET2 I I
RTIME
An RC network may be connected to this pin in order to hold the pin voltage below 2.2V between the peaks of the ringing signal. This pin controls internal I/O power up and activates the partial circuitry needed to determine whether the incoming ring is valid or not. The input is a schmitt trigger input. The output cell structure is an NMOS output. This input pin is connected to the tip side of the twisted pair wires. It is internally biased to 1/2 VDD when the device is in power up mode. This pin must be DC isolated from the line. This input pin is connected to the ring side of the twisted pair wires. It is internally biased to 1/2 VDD when the device is in power up mode. This pin must be DC isolated from the line. This open drain output goes low when a valid ringing signal is detected. When connected to PDWN pin, this pin can be used for auto power up. This open drain output goes low indicating that a valid carrier is present on the line. A hysteresis is built-in to allow for a momentary drop out of the carrier. When connected to PDWN pin, this pin can be used for auto power up. This pin presents the output of the demodulator whenever CDET pin is low. This data stream includes the alternate 1 and 0 pattern, the marking, and the data. At all other times, this pin is held high.
FSK Signal Inputs TIP I
RING
I
Detection Results RDET CDET O O
DOUT
O
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HT9032
Pin Name I/O DOUTC O Description This output presents the output of the demodulator whenever CDET pin is low and when an internal validation sequence has been successfully passed. This data stream does not include the alternate 1 and 0 pattern. This pin is always held high.
Absolute Maximum Ratings
Voltages are referenced to VSS, except where noted. Supply Voltage..............................-0.5V to 6.0V Operating Temperature Range .......0C to 70C All Input Voltages ....................................25mW Storage Temperature Range .....-40C to 150C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol VDD IDD1 IDD2 Parameter Supply Voltage Supply Current Supply Current Test Conditions VDD 3/4 5V 5V Conditions 9032B/C/D 9032F PDWN=0 (3.58MHz OSC on) PDWN=1 and RTIME=0 (3.58MHz OSC on and internal circuits partially on) PDWN=1 and RTIME=1 (3.58MHz OSC off) 3/4 3/4 IOL=1.6mA IOH=0.8mA 3/4 RDET1, RTIME, PDWN
Crystal=3.58MHz, Ta=0~70C Min. 3.5 3.0 3/4 3/4 Typ. 5 5 3.2 1.9 Max. Unit 5.5 5.5 5 2.5 V V mA mA
ISTBY VIL VIH IOL IOH IIN VT-
Standby Current Input Voltage Logic 0 Input Voltage Logic 1 Output Voltage Logic 0 Output Voltage Logic 1 Input Leakage Current, All Inputs Input Low Threshold Voltage
5V 5V 5V 5V 5V 5V 5V
3/4 3/4 0.8V 0.9V -1 2.0
3/4 3/4 3/4 3/4 3/4 3/4 2.3
1 0.2V 3/4 0.1V 3/4 1 2.6
mA VDD VDD VDD VDD mA V
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HT9032
Symbol VT+ Parameter Input High Threshold Voltage Input DC Resistance Test Conditions VDD 5V 5V 5V Conditions RDET1, RTIME, PDWN RDET2 TIP, RING Min. 2.5 1.0 3/4 Typ. 2.75 1.1 500 Max. Unit 3.0 1.2 3/4 V V kW
VTRDET2 Input Threshold Voltage RIN
T IP R IN G RDET1 RDET2 R T IM E PDW N VSS ~
VDD DOUTC DOUT CDET RDET X1 X2
0 .1 m F
HT9032C
3 .5 8 M H z 10M W 30pF
S u p p ly c u r r e n t te s tin g : A ll, e x c e p t P D W N a n d R T IM E , u n w ir e d p in s a r e le ft flo a tin g .
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HT9032
A.C. Characteristics - FSK Detection
VSS=0V, Crystal=3.58MHz, Ta=0 to 70C, 0dBm=0.7746Vrms @ 600W Symbol Parameter Input Sensitivity: TIP, RING S/N Signal to Noise Ratio Band Pass Filter 60Hz 550Hz 2700Hz 3300Hz Carrier Detect Sensitivity tDOSC tSUPD tDAQ tDCH Oscillator Start Up Time Power Up to FSK Signal Set Up Time Carrier Detect Acquisition Time End of Data to Carrier Detect High Test Conditions VDD 5V 5V Frequency Response Relative to 1700Hz @ 0dBm Conditions Min. -40 3/4 Typ. -45 20 -64 -4 -3 -34 -48 2 3/4 14 3/4 Max. 3/4 3/4 Unit dBm dB
5V
3/4
3/4
dB
5V 5V 5V 5V 5V 3/4 3/4 3/4 3/4
3/4 3/4 15 3/4 8
3/4 3/4 3/4 3/4 3/4
dBm ms ms ms ms
2 Sec 0 .5 S e c R in g S ig n a l tD R T IM E 0 1 0 1 0 1 .. 1 DATA 0 .5 S e c
OSC
RDET tS
PDW N
UPD
CDET
tD
AQ
tD Raw DATA
CH
DOUT
DOUTC
C ooked D A TA
X1
3 .5 8 M H z
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HT9032
Functional Description
The HT9032 is designed to be the physical layer demodulator for products targeted for the caller ID market. The data signaling interface should conform to Bell 202, which is described as follows:
* Analog, phase coherent, frequency shift keying * Logical 1 (Mark)=1200+/-12Hz * Logical 0 (Space)=2200+/-22Hz * Transmission rate=1200bps * Data application=serial, binary, * Logical 0 (Space)=2100Hz * Transmission rate=1200bps
Since the band pass filter of the HT9032 can pass the V.23 signal, hence the HT9032 also can demodulate the V.23 signal. Ring detection The data will be transmitted in the silent period between the first and second power ring before a voice path is established. The HT9032 should first detect a valid ring and then perform the FSK demodulation. The typical ring detection circuit of the HT9032 is depicted below. The power ring signal is first rectified through a bridge circuit and then sent to a resistor network that attenuates the incoming power ring. The values of resistors and capacitor given in the figure have been chosen to provide a sufficient voltage at RDET1 pin to turn on the Schmitt Trigger input with approximately a 40 Vrms or greater power ring input from tip and ring. When VT+ of the Schmitt is exceeded, the NMOS on the pin RTIME will be driven to saturation discharging capacitor on RTIME. This will initialize a partial power up, with only the portions of the part involved with the ring signal analysis enabled, including RDET2 pin. With RDET2 pin enabled, a portion of the power ring above 1.2V is fed to the ring analysis circuit. Once the ring signal is qualified, the RDET pin will be sent low.
asynchronous
The interface should be arranged to allow simple data transmission from the terminating central office, to the CPE (Customer Premises Equipment), only when the CPE is in an on-hook state. The data will be transmitted in the silent period between the first and second power ring before a voice path is established. The transmission level from the terminating C.O. will be -13.5dBm+/-1.0. The worst case attenuation through the loop is expected to be -20dB. The receiver therefore, should have a sensitivity of approximately -34.5dBm to handle the worst case installations. The ITU-T V.23 is also using the FSK signaling scheme to transmit data in the general switched telephone network. For mode 2 of the V.23, the modulation rate and characteristic frequencies are listed below:
* Analog, phase coherent, frequency shift keying * Logical 1 (Mark)=1300Hz
PDW N
V
270kW
DD
R T IM E PowerUp L o g ic
0 .2 m F
To B r id g e
470kW 18kW
RDET1
In te rn a l PowerUp L o g ic RDET
RDET2 15kW 1 .2 V
R in g A n a ly s is C ir c u it
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HT9032
Operation mode There are three operation modes of the HT9032. They are power down mode, partial power up mode, and power up mode. The three modes are classified by the following conditions: Modes Power down Partial power up Power up Conditions PDWN=1 and RTIME=1 PDWN=1 and RTIME=0 PDWN=0 <1mA 1.9mA typically 3.2mA typically 1.9mA typically. Once the PDWN pin is below VT-, the part will be fully powered up, and ready to receive FSK. During this mode, the device current will increase to approximately 3.2mA (typ). The state of the RTIME pin is now a dont care as far as the part is concerned. After the FSK message has been received, the PDWN pin can be allowed to return to VDD and the part will return to the power down mode. Current Consumption
Normally, the PDWN pin and the RTIME pin control the operation mode of the HT9032. When both pins are HIGH, the HT9032 is set at the power down mode, consuming less than 1mA of supply current. When a valid power ring arrives, the RTIME pin will be driven below VTand the portions of the part involved in the ring signal analysis are enabled. This is partial power up mode, consuming approximately
Application Circuits
Application circuit 1
T IP V
~
DD
0 .2 m F
0 .0 1 m F
~
200kW 9V
H T1050 0 .1 m F
0 .2 m F R IN G
470kW 0 .0 1 m F 200kW T IP R IN G VDD DOUT
18kW
mC
15kW
PDW N VSS
X1 X2 30pF
3 .5 8 M H z 10M W 30pF
H T 9 0 3 2 B /D
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HT9032
Application circuit 2
T IP V
~
DD
0 .2 m F
0 .0 1 m F
~
200kW 9V
H T1050 0 .1 m F
0 .2 m F R IN G
470kW 20kW 0 .0 1 m F 200kW T IP R IN G RDET1 18kW V 15kW 270kW 0 .2 m F
DD
20kW
VDD DOUTC DOUT CDET RDET X1 X2 30pF mC
RDET2 R T IM E PDW N VSS
3 .5 8 M H z 10M W 30pF
HT9032C
Application circuit 3
T IP V
~
DD
0 .2 m F
0 .0 1 m F
~
200kW 9V
H T1050 0 .1 m F
0 .2 m F R IN G
470kW 0 .0 1 m F 200kW T IP R IN G VDD DOUT CDET 15kW PDW N VSS X1 3 .5 8 M H z 10M W 30pF 30pF 20kW
18kW
mC
HT9032F
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HT9032
Holtek Semiconductor Inc. (Headquarters) No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel: 886-3-563-1999 Fax: 886-3-563-1189 Holtek Semiconductor Inc. (Taipei Office) 5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C. Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Copyright a 2000 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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